Performance Estimation of Low Power and Area-Efficient Parallel Pipelined FFT

Performance Estimation of Low Power and Area-Efficient Parallel Pipelined FFT

We present a novel parallel and pipelined fast Fourier transform (FFT) architecture for high-speed and low-power applications, a critical component in wireless communications and digital signal processors. The new FFT model implements a data-inverted Vedic multiplier in the FFT architecture, which r...

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Bibliographic Details
Main Authors: Surya P, Arunachalaperumal C, Dhilipkumar S
Format: Article
Language:English
Published: Sciendo 2025-06-01
Series:Measurement Science Review
Subjects:
low power fast fourier transform
vedic multiplier
bit inversion technique
look-up table
field programmable gate array
5g application
Online Access:https://doi.org/10.2478/msr-2025-0016
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https://doi.org/10.2478/msr-2025-0016

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