A 1.2-V, 106.4-dB DR Discrete-Time Sigma-Delta Modulator With Feedback Adaptive Cascaded Integrator for Sensor Applications
This innovative research work introduces a novel second-order discrete-time Sigma-Delta (<inline-formula> <tex-math notation="LaTeX">$\Sigma \Delta $ </tex-math></inline-formula>) Analog-to Digital Converter (ADC) design for high performance signal conditioning sens...
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| Format: | Article |
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IEEE
2025-01-01
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| Online Access: | https://ieeexplore.ieee.org/document/11080382/ |
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| author | Ghayur Hussain Nguyen van Quang Muhammad Basim Chang Hyeon Kim Nabeel Ahmad Sung June Byun Kang-Yoon Lee |
| author_facet | Ghayur Hussain Nguyen van Quang Muhammad Basim Chang Hyeon Kim Nabeel Ahmad Sung June Byun Kang-Yoon Lee |
| author_sort | Ghayur Hussain |
| collection | DOAJ |
| description | This innovative research work introduces a novel second-order discrete-time Sigma-Delta (<inline-formula> <tex-math notation="LaTeX">$\Sigma \Delta $ </tex-math></inline-formula>) Analog-to Digital Converter (ADC) design for high performance signal conditioning sensors. A dual-phase noise rejection adaptive frequency gain (AFG) amplifier is designed with an output-stage CMFB circuit to ensure improved stability and performance. These circuits minimize flicker noise, refine noise shaping, and ensure precision, linearity, and stability. They enhance signal integrity, eliminate the need for high-gain amplifiers, and provide optimal loop gain, enabling an efficient modulator design. A highly efficient switched-capacitor feedback DAC enhances the loop filter’s input path. Switched-Capacitor feedback amplifier enables frequency-dependent gain control, signal integration, and differentiation, while miller compensation enhances stability and bandwidth. CMFB circuit is applied at the output of the AFG amplifier to enhance the power supply rejection ratio (PSRR). Low power dynamic latch comparator is used for high-speed, low offset, efficient noise performance and effective clock synchronization. A second-order discrete time modulator model was successfully fabricated using 0.13-<inline-formula> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>m CMOS technology. The structure exhibits an exceptional dynamic range (106.4dB) and 17.38-bit ENOB across 1.95 KHz bandwidth at 2 MHz sampling. The circuit consumes only 1.44 mW using 1.2 V supply. It occupies a minimal chip area of <inline-formula> <tex-math notation="LaTeX">$0.14~\text {mm}^{2}$ </tex-math></inline-formula>. |
| format | Article |
| id | doaj-art-4af6338337904bbfa0970c15b35d2abb |
| institution | Matheson Library |
| issn | 2169-3536 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj-art-4af6338337904bbfa0970c15b35d2abb2025-07-24T23:02:42ZengIEEEIEEE Access2169-35362025-01-011312561812562810.1109/ACCESS.2025.358925011080382A 1.2-V, 106.4-dB DR Discrete-Time Sigma-Delta Modulator With Feedback Adaptive Cascaded Integrator for Sensor ApplicationsGhayur Hussain0https://orcid.org/0009-0002-2189-4712Nguyen van Quang1Muhammad Basim2https://orcid.org/0000-0002-0183-2592Chang Hyeon Kim3Nabeel Ahmad4https://orcid.org/0009-0002-3904-6893Sung June Byun5https://orcid.org/0000-0003-1362-7593Kang-Yoon Lee6https://orcid.org/0000-0001-9777-6953Department of Electrical and Computer Engineering, College of Information and Communication Engineering, Sungkyunkwan University, Suwon, South KoreaDepartment of Electrical and Computer Engineering, College of Information and Communication Engineering, Sungkyunkwan University, Suwon, South KoreaDepartment of Electrical and Computer Engineering, College of Information and Communication Engineering, Sungkyunkwan University, Suwon, South KoreaDepartment of Electrical and Computer Engineering, College of Information and Communication Engineering, Sungkyunkwan University, Suwon, South KoreaDepartment of Electrical and Computer Engineering, College of Information and Communication Engineering, Sungkyunkwan University, Suwon, South KoreaDepartment of Electrical and Computer Engineering, College of Information and Communication Engineering, Sungkyunkwan University, Suwon, South KoreaDepartment of Electrical and Computer Engineering, College of Information and Communication Engineering, Sungkyunkwan University, Suwon, South KoreaThis innovative research work introduces a novel second-order discrete-time Sigma-Delta (<inline-formula> <tex-math notation="LaTeX">$\Sigma \Delta $ </tex-math></inline-formula>) Analog-to Digital Converter (ADC) design for high performance signal conditioning sensors. A dual-phase noise rejection adaptive frequency gain (AFG) amplifier is designed with an output-stage CMFB circuit to ensure improved stability and performance. These circuits minimize flicker noise, refine noise shaping, and ensure precision, linearity, and stability. They enhance signal integrity, eliminate the need for high-gain amplifiers, and provide optimal loop gain, enabling an efficient modulator design. A highly efficient switched-capacitor feedback DAC enhances the loop filter’s input path. Switched-Capacitor feedback amplifier enables frequency-dependent gain control, signal integration, and differentiation, while miller compensation enhances stability and bandwidth. CMFB circuit is applied at the output of the AFG amplifier to enhance the power supply rejection ratio (PSRR). Low power dynamic latch comparator is used for high-speed, low offset, efficient noise performance and effective clock synchronization. A second-order discrete time modulator model was successfully fabricated using 0.13-<inline-formula> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>m CMOS technology. The structure exhibits an exceptional dynamic range (106.4dB) and 17.38-bit ENOB across 1.95 KHz bandwidth at 2 MHz sampling. The circuit consumes only 1.44 mW using 1.2 V supply. It occupies a minimal chip area of <inline-formula> <tex-math notation="LaTeX">$0.14~\text {mm}^{2}$ </tex-math></inline-formula>.https://ieeexplore.ieee.org/document/11080382/Sigma delta modulatorlow-powerfeedback adaptive cascaded integratorsfrequency gain amplifierdata convertershigh precision |
| spellingShingle | Ghayur Hussain Nguyen van Quang Muhammad Basim Chang Hyeon Kim Nabeel Ahmad Sung June Byun Kang-Yoon Lee A 1.2-V, 106.4-dB DR Discrete-Time Sigma-Delta Modulator With Feedback Adaptive Cascaded Integrator for Sensor Applications IEEE Access Sigma delta modulator low-power feedback adaptive cascaded integrators frequency gain amplifier data converters high precision |
| title | A 1.2-V, 106.4-dB DR Discrete-Time Sigma-Delta Modulator With Feedback Adaptive Cascaded Integrator for Sensor Applications |
| title_full | A 1.2-V, 106.4-dB DR Discrete-Time Sigma-Delta Modulator With Feedback Adaptive Cascaded Integrator for Sensor Applications |
| title_fullStr | A 1.2-V, 106.4-dB DR Discrete-Time Sigma-Delta Modulator With Feedback Adaptive Cascaded Integrator for Sensor Applications |
| title_full_unstemmed | A 1.2-V, 106.4-dB DR Discrete-Time Sigma-Delta Modulator With Feedback Adaptive Cascaded Integrator for Sensor Applications |
| title_short | A 1.2-V, 106.4-dB DR Discrete-Time Sigma-Delta Modulator With Feedback Adaptive Cascaded Integrator for Sensor Applications |
| title_sort | 1 2 v 106 4 db dr discrete time sigma delta modulator with feedback adaptive cascaded integrator for sensor applications |
| topic | Sigma delta modulator low-power feedback adaptive cascaded integrators frequency gain amplifier data converters high precision |
| url | https://ieeexplore.ieee.org/document/11080382/ |
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