SCALABLE LOGIC BIST DESIGN AND ANALYSIS FOR ENHANCED TESTING OF COMBINATIONAL CIRCUITS
The paper introduces a scalable Logic Built-In Self-Test (BIST) approach for combinational circuits, utilizing a Bit Swapping Linear Feedback Shift Register (BS-LFSR) as the test pattern generator. Unlike conventional Linear Feedback Shift Registers (LFSRs) that lead to increased dynamic power dissi...
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| Format: | Article |
| Language: | English |
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University of Kragujevac
2025-06-01
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| Series: | Proceedings on Engineering Sciences |
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| Online Access: | https://pesjournal.net/journal/v7-n2/69.pdf |
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| author | Suhas Shirol Rajashekhar Shettar Ramakrishna S Vijay H M |
| author_facet | Suhas Shirol Rajashekhar Shettar Ramakrishna S Vijay H M |
| author_sort | Suhas Shirol |
| collection | DOAJ |
| description | The paper introduces a scalable Logic Built-In Self-Test (BIST) approach for combinational circuits, utilizing a Bit Swapping Linear Feedback Shift Register (BS-LFSR) as the test pattern generator. Unlike conventional Linear Feedback Shift Registers (LFSRs) that lead to increased dynamic power dissipation due to high switching activity, the BS-LFSR reduces the number of transitions, thereby improving power efficiency. The design and implementation were implemented using FPGA and Cadence 180nm technology. Comparative power analysis indicates that the BS-LFSR architecture significantly reduces power consumption compared to traditional LFSR systems. Delay analysis reveals that while pre-synthesis processing times are shorter, post-synthesis data propagation times increase, highlighting a trade-off between synthesis stages. Additionally, area analysis confirms a modest increase in footprint due to integrating a multiplexer in the BS-LFSR, but this is offset by overall enhancements in performance and efficiency. This study demonstrates the potential of BS-LFSR in enhancing the effectiveness of BIST in combinational circuits. |
| format | Article |
| id | doaj-art-f9f2c7042dbe41d984f20d3d57f8cae7 |
| institution | Matheson Library |
| issn | 2620-2832 2683-4111 |
| language | English |
| publishDate | 2025-06-01 |
| publisher | University of Kragujevac |
| record_format | Article |
| series | Proceedings on Engineering Sciences |
| spelling | doaj-art-f9f2c7042dbe41d984f20d3d57f8cae72025-07-02T13:23:04ZengUniversity of KragujevacProceedings on Engineering Sciences2620-28322683-41112025-06-017 21377 138610.24874/PES07.02C.018SCALABLE LOGIC BIST DESIGN AND ANALYSIS FOR ENHANCED TESTING OF COMBINATIONAL CIRCUITSSuhas Shirol 0https://orcid.org/0000-0002-3996-542XRajashekhar Shettar 1Ramakrishna S 2https://orcid.org/0000-0001-9710-6917Vijay H M 3https://orcid.org/0000-0003-1380-2486KLE Technological University, Hubballi, India KLE Technological University, Hubballi, India KLE Technological University, Hubballi, India KLE Technological University, Hubballi, India The paper introduces a scalable Logic Built-In Self-Test (BIST) approach for combinational circuits, utilizing a Bit Swapping Linear Feedback Shift Register (BS-LFSR) as the test pattern generator. Unlike conventional Linear Feedback Shift Registers (LFSRs) that lead to increased dynamic power dissipation due to high switching activity, the BS-LFSR reduces the number of transitions, thereby improving power efficiency. The design and implementation were implemented using FPGA and Cadence 180nm technology. Comparative power analysis indicates that the BS-LFSR architecture significantly reduces power consumption compared to traditional LFSR systems. Delay analysis reveals that while pre-synthesis processing times are shorter, post-synthesis data propagation times increase, highlighting a trade-off between synthesis stages. Additionally, area analysis confirms a modest increase in footprint due to integrating a multiplexer in the BS-LFSR, but this is offset by overall enhancements in performance and efficiency. This study demonstrates the potential of BS-LFSR in enhancing the effectiveness of BIST in combinational circuits.https://pesjournal.net/journal/v7-n2/69.pdfbist- built-in self-testlfsr- linear feedback shift registerbslfsr- bit swapping lfsrtpg- test pattern generatorcut-circuit under testasic’s – application specific ic’s |
| spellingShingle | Suhas Shirol Rajashekhar Shettar Ramakrishna S Vijay H M SCALABLE LOGIC BIST DESIGN AND ANALYSIS FOR ENHANCED TESTING OF COMBINATIONAL CIRCUITS Proceedings on Engineering Sciences bist- built-in self-test lfsr- linear feedback shift register bslfsr- bit swapping lfsr tpg- test pattern generator cut-circuit under test asic’s – application specific ic’s |
| title | SCALABLE LOGIC BIST DESIGN AND ANALYSIS FOR ENHANCED TESTING OF COMBINATIONAL CIRCUITS |
| title_full | SCALABLE LOGIC BIST DESIGN AND ANALYSIS FOR ENHANCED TESTING OF COMBINATIONAL CIRCUITS |
| title_fullStr | SCALABLE LOGIC BIST DESIGN AND ANALYSIS FOR ENHANCED TESTING OF COMBINATIONAL CIRCUITS |
| title_full_unstemmed | SCALABLE LOGIC BIST DESIGN AND ANALYSIS FOR ENHANCED TESTING OF COMBINATIONAL CIRCUITS |
| title_short | SCALABLE LOGIC BIST DESIGN AND ANALYSIS FOR ENHANCED TESTING OF COMBINATIONAL CIRCUITS |
| title_sort | scalable logic bist design and analysis for enhanced testing of combinational circuits |
| topic | bist- built-in self-test lfsr- linear feedback shift register bslfsr- bit swapping lfsr tpg- test pattern generator cut-circuit under test asic’s – application specific ic’s |
| url | https://pesjournal.net/journal/v7-n2/69.pdf |
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