SCALABLE LOGIC BIST DESIGN AND ANALYSIS FOR ENHANCED TESTING OF COMBINATIONAL CIRCUITS
The paper introduces a scalable Logic Built-In Self-Test (BIST) approach for combinational circuits, utilizing a Bit Swapping Linear Feedback Shift Register (BS-LFSR) as the test pattern generator. Unlike conventional Linear Feedback Shift Registers (LFSRs) that lead to increased dynamic power dissi...
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| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
University of Kragujevac
2025-06-01
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| Series: | Proceedings on Engineering Sciences |
| Subjects: | |
| Online Access: | https://pesjournal.net/journal/v7-n2/69.pdf |
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| Summary: | The paper introduces a scalable Logic Built-In Self-Test (BIST) approach for combinational circuits, utilizing a Bit Swapping Linear Feedback Shift Register (BS-LFSR) as the test pattern generator. Unlike conventional Linear Feedback Shift Registers (LFSRs) that lead to increased dynamic power dissipation due to high switching activity, the BS-LFSR reduces the number of transitions, thereby improving power efficiency. The design and implementation were implemented using FPGA and Cadence 180nm technology. Comparative power analysis indicates that the BS-LFSR architecture significantly reduces power consumption compared to traditional LFSR systems. Delay analysis reveals that while pre-synthesis processing times are shorter, post-synthesis data propagation times increase, highlighting a trade-off between synthesis stages. Additionally, area analysis confirms a modest increase in footprint due to integrating a multiplexer in the BS-LFSR, but this is offset by overall enhancements in performance and efficiency. This study demonstrates the potential of BS-LFSR in enhancing the effectiveness of BIST in combinational circuits. |
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| ISSN: | 2620-2832 2683-4111 |