APA (7th ed.) Citation

Shirol, S., Shettar, R., S, R., & M, V. H. (2025). SCALABLE LOGIC BIST DESIGN AND ANALYSIS FOR ENHANCED TESTING OF COMBINATIONAL CIRCUITS. University of Kragujevac.

Chicago Style (17th ed.) Citation

Shirol, Suhas, Rajashekhar Shettar, Ramakrishna S, and Vijay H. M. SCALABLE LOGIC BIST DESIGN AND ANALYSIS FOR ENHANCED TESTING OF COMBINATIONAL CIRCUITS. University of Kragujevac, 2025.

MLA (9th ed.) Citation

Shirol, Suhas, et al. SCALABLE LOGIC BIST DESIGN AND ANALYSIS FOR ENHANCED TESTING OF COMBINATIONAL CIRCUITS. University of Kragujevac, 2025.