Exploring GAA-Nanosheet, Forksheet and GAA–Forksheet Architectures: A TCAD-DTCO Study at 90 nm and 120-nm Cell Height
This study presents a Technology Computer Aided Design (TCAD) and comprehensive Design-Technology Co-Optimization (DTCO) approach to evaluate and enhance power and performance in Gate-All-Around Nanosheet (GAA-Nsh) and Forksheet (Fsh) architectures. The analysis focuses on the impact of active width...
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| Format: | Article |
| Language: | English |
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IEEE
2025-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
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| Online Access: | https://ieeexplore.ieee.org/document/10753294/ |
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| author | Gautam Gaddemane Pieter Schuddinck Krishna Bhuwalka Gerhard Rzepa Gioele Mirabelli Anshul Gupta Jurgen Bommels Philippe Matagne Dmitry Yakimets Hao Wu Lei Hou Geert Hellings Changze Liu |
| author_facet | Gautam Gaddemane Pieter Schuddinck Krishna Bhuwalka Gerhard Rzepa Gioele Mirabelli Anshul Gupta Jurgen Bommels Philippe Matagne Dmitry Yakimets Hao Wu Lei Hou Geert Hellings Changze Liu |
| author_sort | Gautam Gaddemane |
| collection | DOAJ |
| description | This study presents a Technology Computer Aided Design (TCAD) and comprehensive Design-Technology Co-Optimization (DTCO) approach to evaluate and enhance power and performance in Gate-All-Around Nanosheet (GAA-Nsh) and Forksheet (Fsh) architectures. The analysis focuses on the impact of active widths, sheet count, wall properties, and power delivery methods on the effective resistance (Reff) and capacitance (Ceff) of these devices. The research employs simulations of five-stage INVD1 ring oscillators (RO) at various metal pitches (Mx) to extract frequency and power data. Notably, a novel Gate-All-Around Forksheet (GAA-Fsh) structure is introduced, offering enhanced gate control while retaining the advantages of Fsh. The study also explores asymmetric N/PFETs within the Fsh technology, and innovative contacting approaches such as Buried Power Rail (BPR) and Backside Power Rail (BS-PR) with Backside Contact (BSC) to reduce access resistance. Results indicate that GAA-Fsh outperforms traditional GAA-Nsh and Fsh due to reduced <inline-formula> <tex-math notation="LaTeX">${\mathrm { R}}_{\mathrm { eff}}$ </tex-math></inline-formula> and Ceff, although it is process feasible only at larger Mx. At smaller Mx, GAA-Nsh demonstrates higher performance than Fsh at a given sheet width (Wsh), but Fsh, with the advantage of additional Wsh, can match GAA-Nsh performance at larger Wsh. Furthermore, the BPR and BS-PR contacting schemes are found to provide similar performance. This research provides valuable insights into future semiconductor device designs, emphasizing higher performance and efficient scaling. |
| format | Article |
| id | doaj-art-f99b94e7aed54482b0aaf4d88f2cb724 |
| institution | Matheson Library |
| issn | 2168-6734 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Journal of the Electron Devices Society |
| spelling | doaj-art-f99b94e7aed54482b0aaf4d88f2cb7242025-08-01T23:00:28ZengIEEEIEEE Journal of the Electron Devices Society2168-67342025-01-011376978210.1109/JEDS.2024.349809210753294Exploring GAA-Nanosheet, Forksheet and GAA–Forksheet Architectures: A TCAD-DTCO Study at 90 nm and 120-nm Cell HeightGautam Gaddemane0https://orcid.org/0000-0003-0067-8674Pieter Schuddinck1Krishna Bhuwalka2Gerhard Rzepa3https://orcid.org/0000-0002-3711-1957Gioele Mirabelli4https://orcid.org/0000-0001-7060-4836Anshul Gupta5https://orcid.org/0000-0003-4276-5397Jurgen Bommels6https://orcid.org/0000-0002-8761-5213Philippe Matagne7https://orcid.org/0000-0003-0365-2066Dmitry Yakimets8Hao Wu9https://orcid.org/0009-0005-3048-9075Lei Hou10Geert Hellings11https://orcid.org/0000-0002-5376-2119Changze Liu12https://orcid.org/0009-0009-9568-2019imec, Leuven, Belgiumimec, Leuven, BelgiumHuawei Technologies Research and Development, Leuven, BelgiumGlobal TCAD Solutions, Wien, Austriaimec, Leuven, Belgiumimec, Leuven, Belgiumimec, Leuven, Belgiumimec, Leuven, BelgiumHuawei Technologies Research and Development, Leuven, BelgiumHuawei Technologies Research and Development, Leuven, BelgiumHuawei Technologies Research and Development, Leuven, Belgiumimec, Leuven, BelgiumHuawei Technologies Research and Development, Leuven, BelgiumThis study presents a Technology Computer Aided Design (TCAD) and comprehensive Design-Technology Co-Optimization (DTCO) approach to evaluate and enhance power and performance in Gate-All-Around Nanosheet (GAA-Nsh) and Forksheet (Fsh) architectures. The analysis focuses on the impact of active widths, sheet count, wall properties, and power delivery methods on the effective resistance (Reff) and capacitance (Ceff) of these devices. The research employs simulations of five-stage INVD1 ring oscillators (RO) at various metal pitches (Mx) to extract frequency and power data. Notably, a novel Gate-All-Around Forksheet (GAA-Fsh) structure is introduced, offering enhanced gate control while retaining the advantages of Fsh. The study also explores asymmetric N/PFETs within the Fsh technology, and innovative contacting approaches such as Buried Power Rail (BPR) and Backside Power Rail (BS-PR) with Backside Contact (BSC) to reduce access resistance. Results indicate that GAA-Fsh outperforms traditional GAA-Nsh and Fsh due to reduced <inline-formula> <tex-math notation="LaTeX">${\mathrm { R}}_{\mathrm { eff}}$ </tex-math></inline-formula> and Ceff, although it is process feasible only at larger Mx. At smaller Mx, GAA-Nsh demonstrates higher performance than Fsh at a given sheet width (Wsh), but Fsh, with the advantage of additional Wsh, can match GAA-Nsh performance at larger Wsh. Furthermore, the BPR and BS-PR contacting schemes are found to provide similar performance. This research provides valuable insights into future semiconductor device designs, emphasizing higher performance and efficient scaling.https://ieeexplore.ieee.org/document/10753294/DTCOnanosheetForksheetburied power railbackside power deliveryPPA |
| spellingShingle | Gautam Gaddemane Pieter Schuddinck Krishna Bhuwalka Gerhard Rzepa Gioele Mirabelli Anshul Gupta Jurgen Bommels Philippe Matagne Dmitry Yakimets Hao Wu Lei Hou Geert Hellings Changze Liu Exploring GAA-Nanosheet, Forksheet and GAA–Forksheet Architectures: A TCAD-DTCO Study at 90 nm and 120-nm Cell Height IEEE Journal of the Electron Devices Society DTCO nanosheet Forksheet buried power rail backside power delivery PPA |
| title | Exploring GAA-Nanosheet, Forksheet and GAA–Forksheet Architectures: A TCAD-DTCO Study at 90 nm and 120-nm Cell Height |
| title_full | Exploring GAA-Nanosheet, Forksheet and GAA–Forksheet Architectures: A TCAD-DTCO Study at 90 nm and 120-nm Cell Height |
| title_fullStr | Exploring GAA-Nanosheet, Forksheet and GAA–Forksheet Architectures: A TCAD-DTCO Study at 90 nm and 120-nm Cell Height |
| title_full_unstemmed | Exploring GAA-Nanosheet, Forksheet and GAA–Forksheet Architectures: A TCAD-DTCO Study at 90 nm and 120-nm Cell Height |
| title_short | Exploring GAA-Nanosheet, Forksheet and GAA–Forksheet Architectures: A TCAD-DTCO Study at 90 nm and 120-nm Cell Height |
| title_sort | exploring gaa nanosheet forksheet and gaa x2013 forksheet architectures a tcad dtco study at 90 nm and 120 nm cell height |
| topic | DTCO nanosheet Forksheet buried power rail backside power delivery PPA |
| url | https://ieeexplore.ieee.org/document/10753294/ |
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