Design methodology for low-power, low-voltage inductor-less Chua's chaotic oscillator
This paper describes the design and modeling of a low-power, low-voltage Chua's chaotic oscillator using Dynamic Threshold Metal Oxide Semiconductor (DTMOS) technology. The primary active block used for this design is the DTMOS-based Dual-X Second-Generation Current Conveyor (DXCCII), which is...
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| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Elsevier
2025-06-01
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| Series: | MethodsX |
| Subjects: | |
| Online Access: | http://www.sciencedirect.com/science/article/pii/S2215016125002110 |
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| Summary: | This paper describes the design and modeling of a low-power, low-voltage Chua's chaotic oscillator using Dynamic Threshold Metal Oxide Semiconductor (DTMOS) technology. The primary active block used for this design is the DTMOS-based Dual-X Second-Generation Current Conveyor (DXCCII), which is an efficient current-mode active block that dramatically improves circuit performance and efficiency. The nonlinear active element of the Chua circuit, also called the Chua diode, is built using a single DXCCII block. Also, a synthetic inductor using only one DXCCII is used instead of a real inductor is used, which eases the fabrication process. As a result, the complete circuit requires only two DXCCIIs, allowing for an inductor-free design. The suggested circuits, including the Chua diode and Chua circuits, are simulated in PSPICE utilizing TSMC 180 nm CMOS technology. A DTMOS implementation of the DXCCII has been realized and utilized in the simulation with 180 nm CMOS technology. The slopes and the breakpoints of the nonlinear resistors are obtained from the V-I characteristics of Chua's diode, which confirms the theoretical and mathematical predictions. Attractors and chaotic waveforms obtained in the simulation validate the proposed DTMOS-based Chua chaotic oscillator. The circuit uses a bias voltage of ±0.2 V and consumes only 1.58 µW. • A low-power, low-voltage design of Chua's chaotic oscillator using DTMOS technology has been proposed in this paper. • With only two DTMOS-based DXCCIIs, an inductor-less design has been implemented. • The proposed circuit uses a bias voltage of ±0.2 V and consumes only 1.58 µW. |
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| ISSN: | 2215-0161 |