The Design of CMOS-Compatible Plasmonic Waveguides for Intra-Chip Communication
A CMOS-compatible plasmonic waveguide with a metal or metal-like strip sandwiched in-between dielectrics has been proposed for intra-chip communication in the more-than-Moore era. A sequence of numerical models has been presented to evaluate the plasmonic waveguide performance. For device-level cons...
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2020-01-01
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| author | Yan Liu Lu Ding Yu Cao Dongyang Wan Guanghui Yuan Baohu Huang Aaron Voon-Yew Thean Ting Mei Thirumalai Venkatesan Christian A. Nijhuis Soojin Chua |
| author_facet | Yan Liu Lu Ding Yu Cao Dongyang Wan Guanghui Yuan Baohu Huang Aaron Voon-Yew Thean Ting Mei Thirumalai Venkatesan Christian A. Nijhuis Soojin Chua |
| author_sort | Yan Liu |
| collection | DOAJ |
| description | A CMOS-compatible plasmonic waveguide with a metal or metal-like strip sandwiched in-between dielectrics has been proposed for intra-chip communication in the more-than-Moore era. A sequence of numerical models has been presented to evaluate the plasmonic waveguide performance. For device-level consideration, we demonstrated through simulations that Cu (1450 nm pitch) and PLD-TiN (900 nm pitch) plasmonic waveguides symmetrically sandwiched by SiO<sub>2</sub> with much smaller and hence denser interconnects, are promising candidates for use in global wires for the asynchronous communication. This design of plasmonic waveguide can bridge the CMOS circuitry and high-speed communication at optical frequencies within chip. For a system-level assessment, both of them have the same bandwidth throughput of ∼19.8 Gbps. The other performance parameters of Cu and PLD-TiN plasmonic waveguides are respectively, signal latency of ∼<inline-formula><tex-math notation="LaTeX">$0.18\text{ ps}\ $</tex-math></inline-formula>and <inline-formula><tex-math notation="LaTeX">$0.19\text{ ps},$</tex-math></inline-formula> energy dissipation per computing bit of ∼<inline-formula><tex-math notation="LaTeX">$2.5 \times {10^{ - 3}}{\rm{\ fJ}}/{\rm{bit}}$</tex-math></inline-formula> and <inline-formula><tex-math notation="LaTeX">$3.8 \times {10^{ - 3}}{\rm{\ fJ}}/{\rm{bit}}$</tex-math></inline-formula>, and 25% crosstalk coupling length of <inline-formula><tex-math notation="LaTeX">$155{\rm{\ \mu m}}$</tex-math></inline-formula> and <inline-formula><tex-math notation="LaTeX">$125{\rm{\ \mu}} \text{m}$</tex-math></inline-formula>. These findings suggest that plasmonic waveguide for intra-chip communication surpass those of existing electronic interconnects for all the categories of performance parameters. |
| format | Article |
| id | doaj-art-bcd193d7adf242b39d002f3b5e1c5af8 |
| institution | Matheson Library |
| issn | 1943-0655 |
| language | English |
| publishDate | 2020-01-01 |
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| spelling | doaj-art-bcd193d7adf242b39d002f3b5e1c5af82025-07-01T23:55:38ZengIEEEIEEE Photonics Journal1943-06552020-01-0112511010.1109/JPHOT.2020.30241199198892The Design of CMOS-Compatible Plasmonic Waveguides for Intra-Chip CommunicationYan Liu0https://orcid.org/0000-0003-4969-1888Lu Ding1https://orcid.org/0000-0001-8087-2738Yu Cao2Dongyang Wan3https://orcid.org/0000-0001-6810-2183Guanghui Yuan4Baohu Huang5https://orcid.org/0000-0002-2396-3980Aaron Voon-Yew Thean6Ting Mei7https://orcid.org/0000-0001-7756-040XThirumalai Venkatesan8Christian A. Nijhuis9Soojin Chua10Department of Electrical and Computer Engineering, National University of Singapore, SingaporeSingaporeInstitute of Materials Research and Engineering, A<sup>*</sup>STAR (Agency for Science, Technology and Research), SingaporeSingaporeDepartment of Electrical and Computer Engineering, National University of Singapore, SingaporeSingaporeDepartment of Electrical and Computer Engineering, National University of Singapore, SingaporeSingaporeCentre for Disruptive Photonic Technologies, The Photonic Institute, School of Physical and Mathematical Sciences, Nanyang Technological University, SingaporeSingaporeDepartment of Electrical and Computer Engineering, National University of Singapore, SingaporeSingaporeDepartment of Electrical and Computer Engineering, National University of Singapore, SingaporeSingaporeKey Laboratory of Space Applied Physics and Chemistry, Ministry of Education; and Shaanxi Key Laboratory of Optical Information Technology, School of Science, Northwestern Polytechnical University, Xi'an, ChinaNUSNNI-Nanocore, National University of Singapore, SingaporeSingaporeDepartment of Chemistry, National University of Singapore, SingaporeSingaporeDepartment of Electrical and Computer Engineering, National University of Singapore, SingaporeSingaporeA CMOS-compatible plasmonic waveguide with a metal or metal-like strip sandwiched in-between dielectrics has been proposed for intra-chip communication in the more-than-Moore era. A sequence of numerical models has been presented to evaluate the plasmonic waveguide performance. For device-level consideration, we demonstrated through simulations that Cu (1450 nm pitch) and PLD-TiN (900 nm pitch) plasmonic waveguides symmetrically sandwiched by SiO<sub>2</sub> with much smaller and hence denser interconnects, are promising candidates for use in global wires for the asynchronous communication. This design of plasmonic waveguide can bridge the CMOS circuitry and high-speed communication at optical frequencies within chip. For a system-level assessment, both of them have the same bandwidth throughput of ∼19.8 Gbps. The other performance parameters of Cu and PLD-TiN plasmonic waveguides are respectively, signal latency of ∼<inline-formula><tex-math notation="LaTeX">$0.18\text{ ps}\ $</tex-math></inline-formula>and <inline-formula><tex-math notation="LaTeX">$0.19\text{ ps},$</tex-math></inline-formula> energy dissipation per computing bit of ∼<inline-formula><tex-math notation="LaTeX">$2.5 \times {10^{ - 3}}{\rm{\ fJ}}/{\rm{bit}}$</tex-math></inline-formula> and <inline-formula><tex-math notation="LaTeX">$3.8 \times {10^{ - 3}}{\rm{\ fJ}}/{\rm{bit}}$</tex-math></inline-formula>, and 25% crosstalk coupling length of <inline-formula><tex-math notation="LaTeX">$155{\rm{\ \mu m}}$</tex-math></inline-formula> and <inline-formula><tex-math notation="LaTeX">$125{\rm{\ \mu}} \text{m}$</tex-math></inline-formula>. These findings suggest that plasmonic waveguide for intra-chip communication surpass those of existing electronic interconnects for all the categories of performance parameters.https://ieeexplore.ieee.org/document/9198892/CMOS-compatible plasmonic waveguideLong-range SPPhigh integration densitySignal latencyEnergy dissipationLink throughput |
| spellingShingle | Yan Liu Lu Ding Yu Cao Dongyang Wan Guanghui Yuan Baohu Huang Aaron Voon-Yew Thean Ting Mei Thirumalai Venkatesan Christian A. Nijhuis Soojin Chua The Design of CMOS-Compatible Plasmonic Waveguides for Intra-Chip Communication IEEE Photonics Journal CMOS-compatible plasmonic waveguide Long-range SPP high integration density Signal latency Energy dissipation Link throughput |
| title | The Design of CMOS-Compatible Plasmonic Waveguides for Intra-Chip Communication |
| title_full | The Design of CMOS-Compatible Plasmonic Waveguides for Intra-Chip Communication |
| title_fullStr | The Design of CMOS-Compatible Plasmonic Waveguides for Intra-Chip Communication |
| title_full_unstemmed | The Design of CMOS-Compatible Plasmonic Waveguides for Intra-Chip Communication |
| title_short | The Design of CMOS-Compatible Plasmonic Waveguides for Intra-Chip Communication |
| title_sort | design of cmos compatible plasmonic waveguides for intra chip communication |
| topic | CMOS-compatible plasmonic waveguide Long-range SPP high integration density Signal latency Energy dissipation Link throughput |
| url | https://ieeexplore.ieee.org/document/9198892/ |
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