Design and implementation of FinFET and GnrFET based nano arithmetic logic unit
An Arithmetic Logic Unit (ALU) is a fundamental digital circuit within a central processing unit (CPU) or microprocessor that performs arithmetic and logical operations on binary data. However, the conventional complementary metal oxide semiconductor (CMOS) based ALUs were consumed a greater number...
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| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Elsevier
2025-09-01
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| Series: | e-Prime: Advances in Electrical Engineering, Electronics and Energy |
| Subjects: | |
| Online Access: | http://www.sciencedirect.com/science/article/pii/S2772671125001573 |
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| Summary: | An Arithmetic Logic Unit (ALU) is a fundamental digital circuit within a central processing unit (CPU) or microprocessor that performs arithmetic and logical operations on binary data. However, the conventional complementary metal oxide semiconductor (CMOS) based ALUs were consumed a greater number of transistors, power, and delay consumptions. So, this work focused on development of nanotechnology based ALU (Nano-ALU) using Fin field effect transistors (FinFET) and graphene nano-ribbon field effect transistors (GnrFET). Initially, the dynamic path auto-configurable joint-adder-subtractor (DPAJAS) is developed by using multiplexer path selectable full adder (MPFA), enhanced full adder with carry prediction (EFOCP) modules. Then, the dynamic path auto-configurable multiplier is (DPAM) is developed by adopting redundant booth encoding (RBE) and dynamic path auto-configurable adder (DPAA) property of DPAJAS, which contains the multiplexer logics to perform fast switching of data. Finally, the Nano-ALU developed by combining the DPAJAS, DPAM modules, and logical operations. The proposed Nano-ALU outperforms the compared traditional ALUs with an average reduction of approximately 15.7 % in Total Energy Consumption (TEC), about 14.6 % in Total Path Delay (TPD), approximately 15.3 % in Carry Out Rise Delay (CORD), roughly 13.2 % in Carry Out Fall Delay (COFD), approximately 11.0 % in Sum Rise Delay (SRD), about 11.0 % in Sum Fall Delay (SFD), and approximately 6.3 % in Average Power Consumption (APC). |
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| ISSN: | 2772-6711 |