Task Mapping and Scheduling With Uneven Data Partition on Homogeneous and Single-ISA Heterogeneous CPUs in Model-Based Parallelization
Integrated systems comprise diverse tasks, including real-time control and image processing, which must be efficiently executed on embedded system-on-chips with high performance and low power consumption. Multi-core and heterogeneous central processing unit (CPU) architectures, such as Intel...
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| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2025-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/11068991/ |
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| Summary: | Integrated systems comprise diverse tasks, including real-time control and image processing, which must be efficiently executed on embedded system-on-chips with high performance and low power consumption. Multi-core and heterogeneous central processing unit (CPU) architectures, such as Intel’s performance-efficient X86 CPUs, can optimize task execution. Model-based development tools, such as MATLAB/Simulink have further streamlined software design, enabling automatic code generation for embedded systems. This study addresses the challenges of task mapping and scheduling in model-based parallelization (MBP) by focusing on bottleneck tasks that exhibit data parallelism. Control systems may have several dependencies that cause numerous sequential parts and idle times, particularly when the cores exhibit varying performances. Existing methods that rely on even data partitioning may result in suboptimal performance. We propose an ILP task mapping and scheduling framework that introduces uneven data partitioning and optimizes workload balance by filling idle times. Additionally, we present an enhanced MBP workflow that utilizes OpenCV libraries and generates a general pthread code, which improves compatibility across platforms. For random task graphs, the improvement in parallel speedup is approximately 10.02%. For three Simulink models, including a real-world model on single-ISA heterogeneous CPUs, the improvements are 26.25%, 26.55%, and 19.83%. |
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| ISSN: | 2169-3536 |