A Radiation-Hard 8-Channel 15-Bit 40-MSPS ADC for the ATLAS Liquid Argon Calorimeter Readout

A Radiation-Hard 8-Channel 15-Bit 40-MSPS ADC for the ATLAS Liquid Argon Calorimeter Readout

The custom design of a radiation-hardened, 8-channel, 40-MSPS, 15-bit resolution, 14.2-bit dynamic range, 11.4-ENOB ADC data acquisition ASIC fabricated in a commercial 65-nm triple-well CMOS technology is presented. The ADC is developed for and integrates seamlessly into the readout system for the...

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Bibliographic Details
Main Authors: Rui Xu, Jaroslav Ban, Sarthak Kalani, Chen-Kai Hsu, Subhajit Ray, Brian Kirby, Gabriel Matos, Julia Gonski, Andrew C. Smith, Daniel M. Williams, Kiley E. Kennedy, Alan Kahn, Michelle Contreras-Cossio, Lauren Larson, Michael Himmelsbach, Devanshu Panchal, Michael Unanian, Xiangxing Yang, Nan Sun, John Parsons, Timothy R. Andeen, Peter R. Kinget
Format: Article
Language:English
Published: IEEE 2025-01-01
Series:IEEE Open Journal of the Solid-State Circuits Society
Subjects:
DAQ
data acquisition
radiation-hard
radiation-tolerant
system-on-chip
Online Access:https://ieeexplore.ieee.org/document/11017335/
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Summary:The custom design of a radiation-hardened, 8-channel, 40-MSPS, 15-bit resolution, 14.2-bit dynamic range, 11.4-ENOB ADC data acquisition ASIC fabricated in a commercial 65-nm triple-well CMOS technology is presented. The ADC is developed for and integrates seamlessly into the readout system for the ATLAS liquid argon (LAr) calorimeter in the high-luminosity large hadron collider (HLLHC) upgrade at CERN, which will require a total of 364 936 ADC channels. A three-stage MDAC+SAR pipelined ADC architecture was designed to meet the physics requirements and scientific goals of the ATLAS experiment. The ADC is a fully self-contained data acquisition system that includes foreground calibration, digital data processing, digital control, and supporting circuitry. The measured performance shows the ADC achieves a competitive dynamic range and SNDR, and it meets or exceeds the ATLAS analog requirements. Radiation tolerance and scalability design considerations were implemented at the device-, circuit-, and system-level. Radiation-hardening-by-design techniques used include redundancy for digital circuits, the use of MiM capacitors, and a hybrid RC-DAC for the ADC core. The ADC ASIC was demonstrated to be robust against the effects of the intense radiation expected in the HL-LHC experimental environment.
ISSN:2644-1349

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