A Low Complexity Multi-Valued Logic Successor and Predecessor in Nanoelectronics - Yousef Pendashteh; Seied Ali Hosseini (Majlesi Journal of Electrical Engineering, 2024)
Extremely efficient successor and predecessor circuits are suggested in this article using 4 CNTFETs. They have much fewer interconnections and complexity compared to the best previous circuits. The proposed circuits are designed by combining digital and analog techniques for the first time. They can be expanded for all MVLs like ternary, quaternary, pentaternary, and so on. The proposed designs for quaternary logic reduce the transistor count from 25 to 4 in comparison with the best previous works. Interestingly, in MVLs with more level logic, this difference will increase dramatically. This advantage leads to low complexity and costs. The accurate operation and great performance of introduced circuits are illustrated and their superiority is proved. Additionally, a quaternary half-adder is founded on the presented successor and predecessor. The simulation results, which are acquired by comprehensive simulations utilizing Synopsys HSPICE and the 32 nm plenary CNTFET model of Stanford, show that the proposed successor and predecessor circuits with only four transistors work accurately. According to these outcomes, in the proposed half-adder, not only was the transistor count reduced by 32%, but also it had 40% better PDP and 42.05% better EDP in comparison with the best previous work. Also, it is more stable against process variation and robust in a wide range of temperature variations.