Design of an efficient and reconfigurable 1 024 bit large numbers multiplier
Large number multiplication is often used in algorithms such as SM9 encryption. In order to solve the problem of high delay and energy consumption in key circuits in large number multiplication, a reconfigurable 1 024 bit multiplier based on pipeline was designed. By using 64 bit multiplication unit...
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| Format: | Article |
| Language: | Chinese |
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National Computer System Engineering Research Institute of China
2024-03-01
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| Series: | Dianzi Jishu Yingyong |
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| Online Access: | http://www.chinaaet.com/article/3000164112 |
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| author | Su Cheng Xia Hong |
| author_facet | Su Cheng Xia Hong |
| author_sort | Su Cheng |
| collection | DOAJ |
| description | Large number multiplication is often used in algorithms such as SM9 encryption. In order to solve the problem of high delay and energy consumption in key circuits in large number multiplication, a reconfigurable 1 024 bit multiplier based on pipeline was designed. By using 64 bit multiplication units and 128 bit carry ahead addition units, the final result is generated in 20 cycles, alleviating the delay of the addition part in traditional multipliers, achieving circuit multiplexing, and effectively reducing energy consumption. In the SMIC 0.18 μm process library, the critical circuit has a delay of 2.5 ns, a circuit area of 7.03 mm2, and an energy consumption of 576 mW. |
| format | Article |
| id | doaj-art-9e1be2c9a27f446fa62a09e2a0d59ca1 |
| institution | Matheson Library |
| issn | 0258-7998 |
| language | zho |
| publishDate | 2024-03-01 |
| publisher | National Computer System Engineering Research Institute of China |
| record_format | Article |
| series | Dianzi Jishu Yingyong |
| spelling | doaj-art-9e1be2c9a27f446fa62a09e2a0d59ca12025-06-26T02:12:33ZzhoNational Computer System Engineering Research Institute of ChinaDianzi Jishu Yingyong0258-79982024-03-01503313510.16157/j.issn.0258-7998.2341993000164112Design of an efficient and reconfigurable 1 024 bit large numbers multiplierSu Cheng0Xia Hong1North China Electric Power University， Beijing 100096，ChinaNorth China Electric Power University， Beijing 100096，ChinaLarge number multiplication is often used in algorithms such as SM9 encryption. In order to solve the problem of high delay and energy consumption in key circuits in large number multiplication, a reconfigurable 1 024 bit multiplier based on pipeline was designed. By using 64 bit multiplication units and 128 bit carry ahead addition units, the final result is generated in 20 cycles, alleviating the delay of the addition part in traditional multipliers, achieving circuit multiplexing, and effectively reducing energy consumption. In the SMIC 0.18 μm process library, the critical circuit has a delay of 2.5 ns, a circuit area of 7.03 mm2, and an energy consumption of 576 mW.http://www.chinaaet.com/article/3000164112large number multiplicationpipelinewallace treereconfigurable |
| spellingShingle | Su Cheng Xia Hong Design of an efficient and reconfigurable 1 024 bit large numbers multiplier Dianzi Jishu Yingyong large number multiplication pipeline wallace tree reconfigurable |
| title | Design of an efficient and reconfigurable 1 024 bit large numbers multiplier |
| title_full | Design of an efficient and reconfigurable 1 024 bit large numbers multiplier |
| title_fullStr | Design of an efficient and reconfigurable 1 024 bit large numbers multiplier |
| title_full_unstemmed | Design of an efficient and reconfigurable 1 024 bit large numbers multiplier |
| title_short | Design of an efficient and reconfigurable 1 024 bit large numbers multiplier |
| title_sort | design of an efficient and reconfigurable 1 024 bit large numbers multiplier |
| topic | large number multiplication pipeline wallace tree reconfigurable |
| url | http://www.chinaaet.com/article/3000164112 |
| work_keys_str_mv | AT sucheng designofanefficientandreconfigurable1024bitlargenumbersmultiplier AT xiahong designofanefficientandreconfigurable1024bitlargenumbersmultiplier |