Cross‐Point Arrays with Low‐Power ITO‐HfO2 Resistive Memory Cells Integrated on Vertical III‐V Nanowires
Abstract Vertical nanowires with cointegrated metal‐oxide‐semiconductor field‐effect‐transistor (MOSFET) selectors and nonvolatile resistive random access memory (RRAM) cells represent a promising candidate for fast, energy‐efficient, cross‐point memory cells. This paper explores indium‐tin‐oxide‐ha...
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| Format: | Article |
| Language: | English |
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Wiley-VCH
2020-06-01
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| Series: | Advanced Electronic Materials |
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| Online Access: | https://doi.org/10.1002/aelm.202000154 |
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| author | Karl‐Magnus Persson Mamidala Saketh Ram Olli‐Pekka Kilpi Mattias Borg Lars‐Erik Wernersson |
| author_facet | Karl‐Magnus Persson Mamidala Saketh Ram Olli‐Pekka Kilpi Mattias Borg Lars‐Erik Wernersson |
| author_sort | Karl‐Magnus Persson |
| collection | DOAJ |
| description | Abstract Vertical nanowires with cointegrated metal‐oxide‐semiconductor field‐effect‐transistor (MOSFET) selectors and nonvolatile resistive random access memory (RRAM) cells represent a promising candidate for fast, energy‐efficient, cross‐point memory cells. This paper explores indium‐tin‐oxide‐hafnium‐dioxide RRAM cells integrated onto arrays of indium‐arsenide (InAs) vertical nanowires with a resulting area of 0.06 µm2 per cell. For low current operation, an improved switching uniformity over the intrinsic self‐compliant behavior is demonstrated when using an external InAs nanowire MOSFET selector in series. The memory cells show consistent switching voltages below ±1 V and a switching cycle endurance of 106 is demonstrated. The developed fabrication scheme is fully compatible with low‐ON‐resistance vertical III‐V nanowire MOSFET selectors, where operational compatibility with the initial high‐field filament forming is established. Due to the small footprint of a vertical implementation, high density integration is achievable, and with a measured programming energy for 50 ns pulses at 0.49 pJ, the technology promises fast and ultralow power cross‐point memory arrays. |
| format | Article |
| id | doaj-art-8c64a1d5f5c54a609600dc817d51d66d |
| institution | Matheson Library |
| issn | 2199-160X |
| language | English |
| publishDate | 2020-06-01 |
| publisher | Wiley-VCH |
| record_format | Article |
| series | Advanced Electronic Materials |
| spelling | doaj-art-8c64a1d5f5c54a609600dc817d51d66d2025-07-29T18:04:55ZengWiley-VCHAdvanced Electronic Materials2199-160X2020-06-0166n/an/a10.1002/aelm.202000154Cross‐Point Arrays with Low‐Power ITO‐HfO2 Resistive Memory Cells Integrated on Vertical III‐V NanowiresKarl‐Magnus Persson0Mamidala Saketh Ram1Olli‐Pekka Kilpi2Mattias Borg3Lars‐Erik Wernersson4Electrical and Information technology Lund University Box 118 Lund 221 00 SwedenElectrical and Information technology Lund University Box 118 Lund 221 00 SwedenElectrical and Information technology Lund University Box 118 Lund 221 00 SwedenElectrical and Information technology Lund University Box 118 Lund 221 00 SwedenElectrical and Information technology Lund University Box 118 Lund 221 00 SwedenAbstract Vertical nanowires with cointegrated metal‐oxide‐semiconductor field‐effect‐transistor (MOSFET) selectors and nonvolatile resistive random access memory (RRAM) cells represent a promising candidate for fast, energy‐efficient, cross‐point memory cells. This paper explores indium‐tin‐oxide‐hafnium‐dioxide RRAM cells integrated onto arrays of indium‐arsenide (InAs) vertical nanowires with a resulting area of 0.06 µm2 per cell. For low current operation, an improved switching uniformity over the intrinsic self‐compliant behavior is demonstrated when using an external InAs nanowire MOSFET selector in series. The memory cells show consistent switching voltages below ±1 V and a switching cycle endurance of 106 is demonstrated. The developed fabrication scheme is fully compatible with low‐ON‐resistance vertical III‐V nanowire MOSFET selectors, where operational compatibility with the initial high‐field filament forming is established. Due to the small footprint of a vertical implementation, high density integration is achievable, and with a measured programming energy for 50 ns pulses at 0.49 pJ, the technology promises fast and ultralow power cross‐point memory arrays.https://doi.org/10.1002/aelm.202000154indium‐tin‐oxide (ITO)memory arraysnanowiresRRAM |
| spellingShingle | Karl‐Magnus Persson Mamidala Saketh Ram Olli‐Pekka Kilpi Mattias Borg Lars‐Erik Wernersson Cross‐Point Arrays with Low‐Power ITO‐HfO2 Resistive Memory Cells Integrated on Vertical III‐V Nanowires Advanced Electronic Materials indium‐tin‐oxide (ITO) memory arrays nanowires RRAM |
| title | Cross‐Point Arrays with Low‐Power ITO‐HfO2 Resistive Memory Cells Integrated on Vertical III‐V Nanowires |
| title_full | Cross‐Point Arrays with Low‐Power ITO‐HfO2 Resistive Memory Cells Integrated on Vertical III‐V Nanowires |
| title_fullStr | Cross‐Point Arrays with Low‐Power ITO‐HfO2 Resistive Memory Cells Integrated on Vertical III‐V Nanowires |
| title_full_unstemmed | Cross‐Point Arrays with Low‐Power ITO‐HfO2 Resistive Memory Cells Integrated on Vertical III‐V Nanowires |
| title_short | Cross‐Point Arrays with Low‐Power ITO‐HfO2 Resistive Memory Cells Integrated on Vertical III‐V Nanowires |
| title_sort | cross point arrays with low power ito hfo2 resistive memory cells integrated on vertical iii v nanowires |
| topic | indium‐tin‐oxide (ITO) memory arrays nanowires RRAM |
| url | https://doi.org/10.1002/aelm.202000154 |
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