Design and investigation of a delay controlled ALU employing FinFET& CNTFET technologies
The Arithmetic and Logic Unit (ALU) is a crucial logical element of real-time semiconductor devices. Conventional ALUs that are built using Complementary Metal Oxide Semiconductor (CMOS) technology exhibit increased power usage and processing delays. This investigation intends to develop a delay-con...
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Elsevier
2025-09-01
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| Series: | e-Prime: Advances in Electrical Engineering, Electronics and Energy |
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| Online Access: | http://www.sciencedirect.com/science/article/pii/S2772671125001585 |
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| author | Ch JayaPrakash Ashok Battula SurendraBabu Velagaleti |
| author_facet | Ch JayaPrakash Ashok Battula SurendraBabu Velagaleti |
| author_sort | Ch JayaPrakash |
| collection | DOAJ |
| description | The Arithmetic and Logic Unit (ALU) is a crucial logical element of real-time semiconductor devices. Conventional ALUs that are built using Complementary Metal Oxide Semiconductor (CMOS) technology exhibit increased power usage and processing delays. This investigation intends to develop a delay-controlled reconfigurable ALU employing advancements in FinFET (Fin Field Effect Transistor) Carbon Nano Tube Field Effect Transistor and (CNTFET) technology. The first development is the integration of Carry Output Predicted Adders (COPA) along with Carry Input Selective Adders (CISA) employing multiplexing selection circuitry, allowing the development of adders and subtractors with controllable delay. The Delay Controllable Reconfiguration ALU may be built by integrating arithmetic and logical functions. Nanotechnology-based techniques exceed traditional adders and subtractors regarding power efficiency and latency. The outcome results have been obtained with Cadence Virtuoso utilizing 18 nm finFET technological advances, having supply voltages between 0.8 V and 1 V and temperatures between -25 °C and 50 °C. Simulation findings indicate that the suggested 4-bit ALU has remarkable stability. The proposed CNTFET 4-bit Arithmetic Logical Unit (ALU) exhibits a 30 % decrease in power consumption and a 40 % decrease in delay time relative to existing 4-bit ALUs. |
| format | Article |
| id | doaj-art-6f7bcdcc06ec4e3ba81f998c18923f1c |
| institution | Matheson Library |
| issn | 2772-6711 |
| language | English |
| publishDate | 2025-09-01 |
| publisher | Elsevier |
| record_format | Article |
| series | e-Prime: Advances in Electrical Engineering, Electronics and Energy |
| spelling | doaj-art-6f7bcdcc06ec4e3ba81f998c18923f1c2025-06-30T04:09:21ZengElseviere-Prime: Advances in Electrical Engineering, Electronics and Energy2772-67112025-09-0113101051Design and investigation of a delay controlled ALU employing FinFET& CNTFET technologiesCh JayaPrakash0Ashok Battula1SurendraBabu Velagaleti2Department of ECE, Sir C.R. Reddy College of Engineering, Eluru, AndraPradeshDepartment of ECE, Sreyas Institute of Engineering and Technology, HyderabadDepartment of ECE, Sir C.R. Reddy College of Engineering, Eluru, AndraPradeshThe Arithmetic and Logic Unit (ALU) is a crucial logical element of real-time semiconductor devices. Conventional ALUs that are built using Complementary Metal Oxide Semiconductor (CMOS) technology exhibit increased power usage and processing delays. This investigation intends to develop a delay-controlled reconfigurable ALU employing advancements in FinFET (Fin Field Effect Transistor) Carbon Nano Tube Field Effect Transistor and (CNTFET) technology. The first development is the integration of Carry Output Predicted Adders (COPA) along with Carry Input Selective Adders (CISA) employing multiplexing selection circuitry, allowing the development of adders and subtractors with controllable delay. The Delay Controllable Reconfiguration ALU may be built by integrating arithmetic and logical functions. Nanotechnology-based techniques exceed traditional adders and subtractors regarding power efficiency and latency. The outcome results have been obtained with Cadence Virtuoso utilizing 18 nm finFET technological advances, having supply voltages between 0.8 V and 1 V and temperatures between -25 °C and 50 °C. Simulation findings indicate that the suggested 4-bit ALU has remarkable stability. The proposed CNTFET 4-bit Arithmetic Logical Unit (ALU) exhibits a 30 % decrease in power consumption and a 40 % decrease in delay time relative to existing 4-bit ALUs.http://www.sciencedirect.com/science/article/pii/S2772671125001585ALUPower Usage, DelayFinFETCNTFET |
| spellingShingle | Ch JayaPrakash Ashok Battula SurendraBabu Velagaleti Design and investigation of a delay controlled ALU employing FinFET& CNTFET technologies e-Prime: Advances in Electrical Engineering, Electronics and Energy ALU Power Usage, Delay FinFET CNTFET |
| title | Design and investigation of a delay controlled ALU employing FinFET& CNTFET technologies |
| title_full | Design and investigation of a delay controlled ALU employing FinFET& CNTFET technologies |
| title_fullStr | Design and investigation of a delay controlled ALU employing FinFET& CNTFET technologies |
| title_full_unstemmed | Design and investigation of a delay controlled ALU employing FinFET& CNTFET technologies |
| title_short | Design and investigation of a delay controlled ALU employing FinFET& CNTFET technologies |
| title_sort | design and investigation of a delay controlled alu employing finfet cntfet technologies |
| topic | ALU Power Usage, Delay FinFET CNTFET |
| url | http://www.sciencedirect.com/science/article/pii/S2772671125001585 |
| work_keys_str_mv | AT chjayaprakash designandinvestigationofadelaycontrolledaluemployingfinfetcntfettechnologies AT ashokbattula designandinvestigationofadelaycontrolledaluemployingfinfetcntfettechnologies AT surendrababuvelagaleti designandinvestigationofadelaycontrolledaluemployingfinfetcntfettechnologies |