Dual-Mode 2T1C DRAM Process-In-Memory Architecture for Boolean and MAC Operations
With the increasing demand for intelligent memory, the conventional memory system is more and more equipped with computational logic to support simple arithmetic and Boolean operations required by many real-world applications. Such a trend, called ‘Process-In-Memory’ architectu...
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| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2025-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/11095698/ |
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| Summary: | With the increasing demand for intelligent memory, the conventional memory system is more and more equipped with computational logic to support simple arithmetic and Boolean operations required by many real-world applications. Such a trend, called ‘Process-In-Memory’ architecture, tries to utilize most of the memory candidates ranging from the conventional charge-based memory such as SRAM, DRAM, and Flash to the emerging memory devices such as RRAM, PRAM and MRAM. From the application perspective, many researchers are putting efforts to develop efficient memory peripherals with CMOS circuits to support one of two operations: 1) Boolean function, and 2) simple arithmetic operations such as multiplication and accumulation (addition), which is typically referred to as MAC operation. However, there are not many previous works that support both operations in a single system. In this article, we propose a 2T1C DRAM-based PIM architecture that supports dual-mode operation with minimal additional hardware. The proposed architecture has been fabricated using a commercial 65nm CMOS technology and successfully proves that the target operations are performed with a reasonably good accuracy. |
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| ISSN: | 2169-3536 |