A Low-Power Read-Decoupled Radiation-Hardened 16T SRAM for Space Applications
Advancements in CMOS technology have significantly reduced both transistor dimensions and inter-device spacing, leading to a lower critical charge at sensitive nodes. As a result, SRAM cells used in space applications have become increasingly vulnerable to single-event upset (SEU) caused by the hars...
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| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2025-06-01
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| Series: | Applied Sciences |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2076-3417/15/12/6536 |
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| Summary: | Advancements in CMOS technology have significantly reduced both transistor dimensions and inter-device spacing, leading to a lower critical charge at sensitive nodes. As a result, SRAM cells used in space applications have become increasingly vulnerable to single-event upset (SEU) caused by the harsh radiation environment. To ensure reliable operation under such conditions, radiation-hardened SRAM designs are essential. In this paper, we propose a low-power read-decoupled radiation-hardened 16T (LDRH16T) SRAM cell to mitigate the effects of SEU. The proposed cell is evaluated against several state-of-the-art soft-error-tolerant SRAM designs, including QUCCE12T, WE-QUATRO, RHBD10T, SIS10T, EDP12T, SEA14T, and SAW16T. Simulations are conducted using a 90 nm CMOS process at a supply voltage of 1 V and a temperature of 27 °C. Simulation results show that LDRH16T successfully recovers its original state after injection at all sensitive nodes. Furthermore, since its storage nodes are decoupled from the bit lines during read operations, the proposed cell achieves the highest read stability among the compared designs. It also exhibits superior write ability, shorter write delay, and significantly lower hold power consumption. In addition, LDRH16T demonstrates excellent overall performance across key evaluation metrics and proves its capability for reliable operation in space environments. |
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| ISSN: | 2076-3417 |