Comparative analysis of adders hardware implementation on FPGA - Nikolay Ivanovich Chervyakov; Pavel Alekseyevich Lyakhov; Maria Vasilevna Valueva; O. V. Krivolapova (Наука. Инновации. Технологии, 2022)
In this work we considered two types of adders for addition of two binary numbers implementation: carry propagate adders and parallel-prefix adders. In this article simulation on FPGA for both architectures and their comparative analysis is made. Simulation results for 4, 8, 16 and 32-bits circuits showed that parallel-prefix architecture using gives the gain in speed up to 41% compared to sequential architecture through increasing the hardware costs up to 71%. Parallel-prefix adders should use the for those applications, in which the maximization of speed is the main objective. On the other hand, carry propagate adder is better for hardware costs and power consumption decrease.